#4996`stop(msg)` does not emit correct verilog

Type of issue: Bug Report

Please provide the steps to reproduce the problem:

//> using scala "2.13.12"
//> using dep "org.chipsalliance::chisel:6.7.0"
//> using plugin "org.chipsalliance:::chisel-plugin:6.7.0"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"

import chisel3._
// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._
import _root_.circt.stage.ChiselStage

class Foo extends Module {
  val a = IO(Input(Bool()))
  when (a) {
    stop("done")
  }
}

object Main extends App {
  println(
    ChiselStage.emitSystemVerilog(
      gen = new Foo,
      firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
    )
  )
}

What is the current behavior?

The above generates the following Verilog:

// Generated by CIRCT firtool-1.62.1
// Standard header to adapt well known macros for prints and assertions.

// Users can define 'PRINTF_COND' to add an extra gate to prints.
`ifndef PRINTF_COND_
  `ifdef PRINTF_COND
    `define PRINTF_COND_ (`PRINTF_COND)
  `else  // PRINTF_COND
    `define PRINTF_COND_ 1
  `endif // PRINTF_COND
`endif // not def PRINTF_COND_

module Foo(
  input clock,
        reset,
        a
);

  `ifndef SYNTHESIS
    always @(posedge clock) begin
      if ((`PRINTF_COND_) & a & ~reset)
        $fwrite(32'h80000002, "done");
    end // always @(posedge)
  `endif // not def SYNTHESIS
endmodule

What is the expected behavior?

A $finish is missing. If we change the stop("done") to just a stop(), it does the right thing:

    always @(posedge clock) begin
      if ((`STOP_COND_) & a & ~reset)
        $finish;
    end // always @(posedge)

What is the use case for changing the behavior?

stop(msg) should print the message and stop the simulation as per the API doc.